1. Field of the Invention
The present invention relates to telecommunications devices and, in particular, to a digital 2B1Q transmitter circuit which meets the high precision and linearity time domain response requirements of the U-interface ISDN standard.
2. Discussion of the Prior Art
Communication over a digital subscriber line (DSL) in the evolving Integrated Services Digital Network (ISDN) requires error-free transmission of binary data with the alphabet B=(0, 1) at a bit rate of 160 kg/sec. Line impairments, such as attenuation/dispersion and cross-talk noise, corrupt the received signal at the receive end of the DSL and introduce error.
To counter these impairments and to remove error, different modulation techniques can be employed that result in bandwidth reduction of the transmitted signal. The modulation technique adopted by American National Standards Institute (ANSI) for use over the DSL is called 2B1Q line coding. According to this coding technique, successive pairs of binary data B are one-to-one mapped onto successive units of quaternary symbols with alphabet Q=(-3, -1, +1, +3) and transmitted as a corresponding voltage level at half the rate of the binary sequence. Therefore, an incoming binary stream B with bit rate of 160 kbit/sec. is converted into a quaternary stream Q with symbol rate of 80 kbit/sec. and then transmitted over the DSL.
There are two basic approaches to the design of transmitter circuits, recursive and non-recursive.
A typical example of the recursive approach is to feed square wave pulses, amplitude modulated according to 2B1Q levels, through a linear low-pass filter.
The recursive approach is not generally utilized for echo canceller applications for the following reasons. First, if a continuous filter approach is utilized, it is difficult to control the pulse envelope because of roll-off frequency variations. If the frequency controlling elements, such as resistors and capacitors, are locked to an on-chip reference, linearity can be a problem. Furthermore, cost and yield are also known factors. If a switched-capacitor approach is utilized, then two filters are required, one to provide the basic pulse shaping and the other for anti-alias filtering.
In general, in recursive filters, the trailing portion of the pulse after filtering extends too many baud periods due to the recursive nature of the filters. This increases the number of taps in the echo canceller circuit. In addition, the summation of pulse tails demands an extended dynamic range for the transmitter driver to handle the voltage swings. This stresses the linearity/cost/power design requirements of the driver circuit.
Furthermore, the amount of pulse undershoot after filtering normally is significant compared to the pulse template. Undershoot as high as 5% to 8% of the main pulse amplitude has been observed. Since 12% is the limit for the undershoot template, there is little margin left for the design of the line transformer.
Additionally, the slope (dV/dt) of the filtered transmitter pulse normally is steeper than the pulse slope generated from a non-recursive circuit. A high order, low-Q filter is the only solution if cost is not a major concern (pre-processing in the drive signal is also a solution, but falls into the non-recursive category). The high dV/dt signal leaves less jitter margin for the timing circuit that drives the transmitter/filter circuits. In some cases, a "differential canceller" is required to handle this type of impairment.
The non-recursive approach also suffers from some disadvantages. First, silicon area for integrating a transversal filter is usually high compared to other approaches. Pre-processing the drive signal using a current-slewing method has a wide performance distribution due to process variation; usually, this is not a practical solution for silicon implementation. A ROM look-up method always requires a high resolution digital-to-analog converter (DAC) because of the required summation of vectors in the modulation process. It is costly to build a high resolution DAC with high degree of linearity. For example, for eight bits or more, a 3-bit DAC is the theoretical minimum for any approach including filtering methods, the combination yielding five levels: (+3, +1, 0, -1, -3).